1. Field of the Invention
The present invention disclosed in this specification relates to a semiconductor device, particularly to the structure in which wirings separately provided over and under an insulating layer are connected.
2. Description of the Related Art
Multilevel interconnection is known as a wiring structure of a semiconductor integrated circuit. Multilevel interconnection needs contact holes for connecting a lower wiring and an upper wiring between which an interlayer insulating film is placed. Issues involved with multilevel interconnection include the problem of step coverage of wiring material (metal material) which fills a contact hole. If the step coverage of the wiring material which fills the contact hole is poor, a problem arises in that disconnection occurs and the upper and lower wirings cannot be connected to each other, for example.
As means to solve such a problem, a method in which a metal plug is selectively grown in a contact hole, and then an interlayer insulating film and the metal plug is planarized by chemical mechanical polishing (Patent Literature 1); a method in which an embedded metal layer is formed in a contact hole by plating (Patent Literature 2); and the like have been known.
[Patent Literature 1] Japanese Published Patent Application No. JP8-222631
[Patent Literature 2] Japanese Published Patent Application No. JP11-163129